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Si4322
Output and FIFO Mode Command
bit
15
1
14
1
13
0
12
0
11
1
10
1
9
1
8
0
7
f3
6
f2
5
f1
4
f0
3
s1
2
s0
1
ff
0
fe
POR
CE87h
Bit 7-4 < f3 : f0 >:
Bit 3-2 < s1 : s0 >:
FIFO IT level. The FIFO generates IT when number of the received data bits reaches this level.
Select the input of the FIFO fill start condition:
s1
s0
0
0
1
1
0
1
0
1
VDI
Sync. Word
Sync. Word
Always
DATA (from data filter)
CLK (from clock recovery)
VDI
0
FIFO WRITE Logic
(simplified)
FIFO_WRITE_DATA
FIFO_WRITE_CLK
CR_LOCK
DQD
VDI
Q
Sync. Word
Detector
EN
nRES
SYNC. WORD
SYNC. WORD
logic HIGH
s0*
1
2
3
M
U
X
FIFO_WRITE_EN
s1*
fifo fill enable*
fifo enable*
fifo enable*
Pad DATA
I/O Port
DIRECTION
nFIFO_RESET
NOTE:
* For details see the Output and FIFO Mode Command
Not e :
VDI (Valid Data Indicator) see further details in Receiver Control Word , Synchron word in microcontroller mode is 2DD4h.
Bit 1 < ff >:
Bit 0 < fe >:
Enables FIFO fill after synchron word reception. FIFO fill stops when this bit is cleared.
Enables the 48 bit deep FIFO mode. To clear the counter of the FIFO, it has to be set to zero.
Not e :
To restart the synchron word reception, bit 1 should be cleared and set.
This action will initialize the FIFO and clear its content.
Bit 0 modifies the function of DATA pin and DCLK pin. The DATA pin will become input (nFFS) if fe is set to 1. If the chip is
used in FIFO mode, do not allow this to be a floating input.
14
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